Dynamic termination logic driver with improved impedance control

ABSTRACT

A driver capable of launching signals into a transmission line and of terminating signals at a receiver end of the transmission line includes within the driver a circuit for controlling the output impedance and a circuit for controlling the output slew rate. Accordingly, a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance. The driver includes a pull up circuit coupled to receive at least one of a plurality of control codes. The pull up circuit includes pull up output circuit and an impedance control buffer circuit, a parallel pull up circuit, the parallel pull up circuit and the pull up output circuit being controllable to adjust the impedance of the pull up circuit. The driver also includes a pull down circuit coupled to receive at least one of the plurality of control codes. The pull down circuit includes at least one pull down output circuit and a parallel pull down circuit, the parallel pull down circuit being controllable to adjust the impedance of the pull down circuit. The output impedance of the driver is further controlled during transitional phases of turning on and turning off the pull down circuit and the pull up circuit under a plurality of process, voltage and temperature (PVT) conditions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of application Ser. No. 09/398,868 filed Sep. 20,1999, now U.S. Pat. No. 6,420,913.

This application relates to co-pending U.S. patent application Ser. No.09/399,450, filed on Sep. 20, 1999, entitled A Method for a DynamicTermination Logic Driver with Improved Impedance Control and namingMichael A. Ang, Alexander D. Taylor, Jonathan E. Starr, and Sai V.Vishwanthaiah as inventors, the application being incorporated herein byreference in its entirety.

This application relates to co-pending U.S. patent application Ser. No.09/398,872, filed on Sep. 20, 1999, entitled A Method for a DynamicTermination Logic Driver with Improved Slew Rate Control and namingMichael A. Ang, Alexander D. Taylor, Jonathan E. Starr, and Sai V.Vishwanthaiah as inventors, the application being incorporated herein byreference in its entirety.

This application relates to co-pending U.S. patent application Ser. No.09/399,453, filed on Sep. 20, 1999, entitled A Dynamic Termination LogicDriver with Improved Slew Rate Control and naming Michael A. Ang,Alexander D. Taylor, Jonathan E. Starr, and Sai V. Vishwanthaiah asinventors, the application being incorporated herein by reference in itsentirety.

This application relates to co-pending U.S. patent application Ser. No.09/326,964, filed on Jun. 7, 1999, entitled Output Driver With ImprovedImpedance Control and naming Michael A. Ang, Alexander D. Taylor,Jonathan E. Starr, and Sai V. Vishwanthaiah as inventors, theapplication being incorporated herein by reference in its entirety.

This application relates to co-pending U.S. patent application Ser. No.09/327,220, filed on Jun. 7, 1999, entitled Method For An Output DriverWith Improved Impedance Control and naming Michael A. Ang, Alexander D.Taylor, Jonathan E. Starr, and Sai V. Vishwanthaiah as inventors, theapplication being incorporated herein by reference in its entirety.

This application relates to co-pending U.S. patent application Ser. No.09/326,909, filed on Jun. 7, 1999, entitled Output Driver With ImprovedSlew Rate Control and naming Michael A. Ang, Alexander D. Taylor,Jonathan E. Starr, and Sai V. Vishwanthaiah as inventors, theapplication being incorporated herein by reference in its entirety.

This application relates to co-pending U.S. patent application Ser. No.09/327,057, filed on Jun. 7, 1999, entitled Method For An Output DriverWith Improved Slew Rate Control and naming Michael A. Ang, Alexander D.Taylor, Jonathan E. Starr, and Sai V. Vishwanthaiah as inventors, theapplication being incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to driver circuits and more particularlyto driver circuits for use in information processing systems.

2. Description of the Related Art

In computer and information processing systems, various integratedcircuit chips must communicate digitally with each other over commonbuses. The signal frequency at which this communication occurs can limitthe performance of the overall system. Thus, the higher thecommunication frequency, the better. The maximum frequency at which asystem communicates is a function not only of the time that it takes forthe electromagnetic wavefronts to propagate on the bus from one chip toanother, but also of the time required for the signals to settle tolevels that can be reliably recognized at the receiving bus nodes asbeing HIGH or LOW, referred to as the settling time.

There are several factors which affect the settling time of a signal.For example, the “slew rate” of the launched signal, i.e., the rate atwhich the voltage level of the launched signal changes from one level toanother, is one factor which affects the settling time of the signal.The oscillations in the voltage level of the signal (i.e., the“ringing”) due to the effects of package inductance, pad capacitance andother “parasitics” is another factor which affects the settling time ofthe signal. Ringing due to reflections from impedance mismatches withinthe bus system is another factor which affects the settling time of thesignal. The voltage level of the launched signal relative to the overallsignal swing (i.e., the difference between high and low voltage levelsof the signal) is another factor which affects the settling time of thesignal. The effectiveness of the termination of the bus is anotherfactor which affects the settling time of the signal.

The operating characteristics of transistors such as CMOS transistors,from which drivers are typically constructed, change under a variety ofconditions, often referred to as process, voltage, temperature (PVT)variations. PVT variations may be conceptualized as a box across whichthe operating characteristics of the trnnsistors move. One of ordinaryskill in the art will appreciate that the three characteristics,process, voltage and temperature can be visualized as a threedimensional graph with a “slow corner” identifying a point when thethree characteristics affect operating conditions, and a “fast corner”identifying a point when the three characteristics do not greatly affectoperating conditions. For example, the operating characteristics maymove from a fastest corner of PVT variations to a slowest corner of PVTvariations, and everywhere in between. More specifically, the operatingcharacteristics due to PVT variations may change with variations inmanufacturing process as well as with variations in operating conditionssuch as junction temperature and supply voltage levels. The operatingcharacteristics may also change with variations of voltage differencesacross the transistor terminals of the driver; the voltage differencesmay change as the voltage level at the output node of the driverchanges.

If inadequate compensation is made for these variations, the output slewrate and output impedance of the driver may vary substantially within aparticular driver as well as from driver to driver on a chip.

Another characteristic that is desirable to control within a driver iscrowbar current. The crowbar current is the current that flows directlybetween the supply rails of a driver through the pull up and pull downunits of a driver if both units are enabled simultaneously. Having highcrowbar current may cause the driver to consume more power thannecessary to provide adequate driver performance.

It is known to provide drivers having different terminationcharacteristics. For example, a High Speed Transceiver Logic (HSTL) typedriver, may be designed to terminate at the driver end of a transmissionline; a Dynamic Termination Logic (DTL) type driver may be designed toterminate at the receiver end of a transmission line. Each of thesedriver types has characteristics that affect the driver when aparticular type is chosen for a design. What is needed is a driver thatprovides adequate performance under the different characteristics thataffect the driver design.

SUMMARY OF THE INVENTION

A driver for terminating signals at a receiver end of a transmissionline controls output impedance and includes within the driver animpedance control circuit and a slew rate control system. Accordingly, adesired output impedance can be advantageously established andmaintained over a wide range of variations in operating conditions,manufacturing processes and output voltage levels. Such a driver alsoadvantageously limits any crowbar current, thereby reducing the overallpower consumption of the driver with little, if any, degradation ofdriver performance. The driver includes a pull up circuit coupled toreceive at least one of a plurality of control codes. The pull upcircuit includes pull up output circuit and an impedance control buffercircuit, a parallel pull up circuit, the parallel pull up circuit andthe pull up output circuit being controllable to adjust the impedance ofthe pull up circuit. The driver also includes a pull down circuitcoupled to receive at least one of the plurality of control codes. Thepull down circuit includes at least one pull down output circuit and aparallel pull down circuit, the parallel pull down circuit beingcontrollable to adjust the impedance of the pull down circuit. Theoutput impedance of the driver is further controlled during transitionalphases of turning on and turning off the pull down circuit and the pullup circuit under a plurality of process, voltage and temperature (PVT)conditions.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerousobjects, features, and advantages made apparent to those skilled in theart by referencing the accompanying drawings.

FIG. 1 shows a block diagram of an information handling system having adriver circuit in accordance with the present invention.

FIG. 2 shows a block diagram of the driver circuit in accordance withthe present invention.

FIG. 3 shows a block diagram of the predriver of the pull up circuit forthe driver circuit of FIG. 2.

FIG. 4 shows a schematic block diagram of a parallel bit pull up circuitof the pull up circuit of FIG. 3.

FIG. 5 shows a schematic block diagram of pull up output circuit shownin FIG. 4.

FIG. 6 shows a schematic of an inverter cell for the pull up outputcircuit shown in FIG. 5 for the driver circuit of FIG. 2.

FIG. 7 shows a schematic block diagram of a parallel bit pull downcircuit of the pull up circuit of FIG. 7.

FIG. 8 shows block diagram of a parallel pull up circuit shown in FIG.5.

FIG. 9 shows a schematic of a slew rate control capacitor circuit shownin FIG. 5.

FIG. 10 shows a schematic of pull down multiplexor circuits shown inFIG. 2.

FIG. 11 shows a block diagram of a pull down circuit shown in FIG. 2.

FIG. 12 shows a schematic of a generic pull down output circuit of pulldown output blocks shown in FIG. 11.

FIG. 13 shows a schematic block diagram of the parallel pull downcircuit shown in FIG. 12.

FIG. 14 shows a schematic of a generic supplemental pull down circuit ofFIG. 13.

FIG. 15 shows a schematic of a slew rate control capacitor circuit shownin FIG. 12.

FIG. 16 shows a schematic of a slowing rate circuit shown in FIG. 11.

FIG. 17 shows a current-voltage curve for the pull up output circuit.

FIG. 18 is a current vs. time graph showing three ways in which thecurrent ramps with time.

The use of the same reference symbols in different drawings indicatessimilar or identical items.

DETAILED DESCRIPTION

Overview

Referring to FIG. 1, information handling system 100 includes aplurality of components 102 such as processor 102 a, memory controller102 b, and I/O controller 102 c. It will be appreciated that thesecomponents 102 may be any type of component commonly found in aninformation handling system. Each of these components 102 is generallyconfigured as an individual integrated circuit chip. However, it isknown to combine various components into a single integrated circuitchip. Components 102 are coupled via bus 104. Bus 104 includes aplurality of parallel lines which are coupled to individual signaloutputs of each of the components 102.

Each component 102 includes a plurality of circuits 108, includinginput/output circuits and may include output only circuits. Theplurality of circuits 108 are coupled to individual signal paths of bus104. Each circuit 108 may include a receiver circuit 109 and a drivercircuit 110. Component 102 also includes impedance control circuit 112which may be coupled to each driver circuit 110. Impedance controlcircuit 112 controls the output impedance of each driver and isappropriate for bus systems that are terminated at the source only andare “open-circuited” at the destination nodes or for bus systemsterminated at the destination nodes such as dynamic termination logicbus systems.

In addition to the impedance control circuit 112, as more fullydescribed below, circuitry in the driver circuits 110, including a pullup circuit and a pull down circuit, maintain control over the operatingcharacteristics including output slew rate as well as crowbar current.

In operation, in driver circuits 110, control can be exercised overcertain operating characteristics such as output impedance, output slewrate, and “crowbar” current. It is possible to control the outputimpedance of the driver circuits 110 even though the operatingconditions of the transistors inside the driver circuits 110 vary withthe manufacturing process, supply voltage, and temperature (PVT) andwith changes in the voltages across the terminals of the transistorsvoltage levels.

One of skill in the art will appreciate that driver circuits 110 areappropriate for bus systems in which, driver circuits 110 send signalsonto a transmission line, and there may be either one or more receivingnodes each having a 50-ohm termination resistance or other resistanceconnected between the line and VDDO. Accordingly the steady-state “high”voltage at the output of the driver circuits 110 is VDDO, and thesteady-state “low” voltage will be approximately (within 10% of) VDDO/2.Therefore, for purposes of example only, if there is only onetermination resistance, the active driver 110 must be set to have apull-down resistance of 50 ohms, and, if there are two, the activedriver 110 must be set to have a pull-down resistance of 25 ohms. One ofordinary skill in the art appreciates that other termination resistancesand transmission line impedances are feasible.

Although the discussion above relates to driver circuits in general, thepresent invention relates to DTL type drivers. Improved HSTL typedrivers are the subject of cross-referenced patent applications Ser.Nos. 09/326,964, 09/327,220, 09/326,909, 09/327,057, filed Jun. 7, 1999,and are incorporated herein in their entireties. Referring now to DTLdriver systems, during operation of a DTL system, transient periodsoccur during which the voltage level at the output node of the driver110 will go outside of the range stated above, i.e. VDDO and VDDO/2. Oneof ordinary skill in the art will appreciate that in situations in whichthe driver 110 is not “tri-stated” (giving a very-high outputimpedance), the voltages at the output node may range from as low as VSSto as high as 1.25*VDDO, and could reach higher voltages due to “bounce”parasitics. Therefore, the driver 110 operating characteristics, such asoutput impedance and output slew rate, must be controlled over thisrange of possible output voltages.

There are significant design differences between HSTL driver systems andDTL driver systems. Much of the functioning of the HSTL driver describedin the referenced patent applications is symmetric between pulling highand pulling low. For example, the signal swing is from VSS to VDDO, andsignals are launched by the turning on of the appropriate outputcircuit.

In contrast, the design of the DTL driver system herein is asymmetrical.For example, the signal swing is from VDDO/2 to VDDO, some signals arelaunched by the turning on of an output, and some signals are launchedby the turning off of an output circuit. In addition, when the logic ofa bus to driver 110 is low, dc-current flows through the pull downcircuit 204 of the driving-end and through the pull up circuit 202 ofthe receiving end(s). To accommodate these asymmetries between pull upand pull down functions, there are corresponding asymmetries in thedesign of the overall driver, as described below.

Structure

FIGS. 2-16 portray the basic structural components of the driver circuit110, including both the pull up circuit 202 and the pull down circuit204.

Referring to FIG. 2, driver circuit 110 includes pull up circuit 202 anda pull down circuit 204 as well as other components, including controlcircuit 222, which provides logical outputs di_up 214, di_dn 216, anddi25_dn 224. Control circuit 222 receives a data signal 212, an outputenable circuit oe 220, an up_open signal 208, and a down_25 210 signal.Each of the pull up circuit 202 and the pull down circuit 204 of drivercircuit 110 receives a high voltage input supply (VDDO) and is coupledto a ground reference voltage (not shown). Pull up circuit 202 receivesa set of control signals cbu<8:1> 225 and cbd_s<8:1> 226, of whichsignal set cbu<8:1> 225 is provided by a circuit outside the driver 110to pull up circuit 202. Pull down circuit 204 also receives a set ofcontrol signals cbd<8:1> 207 which is provided by a circuit outside thedriver 110 to pull down circuit 204.

Also shown in FIG. 2 are three multiplexor circuits 230, 240, and 250,which provide data signals to the pull down and pull up circuits 204 and202.

Referring now to FIG. 3, multiplexor circuit 230 is shown in furtherdetail. Multiplexor circuit 230 provides output default circuitryincluding inverting circuits 301, and 303, as well as multiplexingtransistors. Inverting circuit 303 includes inverting transistor pair351 and inverting transistor pair 353. Inverting circuit 301 includesinverting transistor pair 323 and inverting transistor pair 321. Themultiplexing transistors include NMOS transistor 302, PMOS transistors312, 304, 306, and 316, and NMOS transistors 308, 310, 314, and 318.

Referring now to FIG. 4, the pull up circuit 202 is shown in blockdiagram form. Two inputs to the pull up circuit 202, i.e., high drivingsignal h_or_z_n 203 and low driving signal l_or_z_n 205 are receivedfrom multiplexor circuit 230, discussed above. As shown, pull up circuit202 includes an impedance control buffer circuit 410 and a pull upoutput circuit 420.

Referring to FIG. 5, a schematic of the pull up output circuit 420 isshown in further detail showing that the paths for h_or_z_n 203 andl_or_z_n 205 are received from multiplexor circuit 230, as well assignals cbd_s<8:1> 226 and cbu<8:1> 424. FIG. 5 shows inverting buffercell 510, slew rate control capacitor circuit 550, parallel pull upcircuit 530, and output control circuitry. The output control circuitryincludes base bit pull up output element 508, which includes PMOStransistor 526 and NMOS transistor 528. Transistors 518, 516, 512, 514and PMOS capacitor 522, together form pull up gate voltage controlcircuit 501.

Referring now to FIG. 6, inverting buffer cell 510 is shown in detail.FIG. 6 includes a parallel set of NMOS transistors 600, NMOS transistor690, and an inverting transistor pair including PMOS transistor 620 andNMOS transistor 622.

FIG. 7 shows a block diagram of parallel pull up circuit 530 shown inFIG. 5. FIG. 7 shows the parallel configuration of individualsupplemental pull up circuits 700. As shown, parallel pull up circuit530 receives signals h_or_z_n 203 and l_or_z 506 and control signalscb<8:1> 424.

FIG. 8 shows a schematic of a single supplemental pull up circuit 700,including supplemental pull up output element 808, a gate voltagecontrol PMOS capacitor 860, and a bit control circuit 850. Supplementalpull up output element 808 includes PMOS transistor 826 and NMOStransistor 828. Bit control circuit 850 includes transmission gates 820and 830 as well as PMOS 854, NMOS 852 and inverter 804.

FIG. 9 is a schematic of slew rate control capacitor circuit 550. FIG. 9includes a parallel set of NMOS capacitors 900 and a parallel set ofPMOS transistors 910 coupled to the gates of capacitors 900.

FIG. 10 relates to the pull down function of driver 110, showing asingle schematic representing both multiplexors 240 and 250 shown inFIG. 2. FIG. 10 is similar to FIG. 3, and includes inverting circuits1001 and 1003. Inverting circuit 1001 further includes invertingtransistor pairs 1072 and 1074. Inverting circuit 1003 includesinverting transistor pair 1086 and NMOS transistor 1092. Also includedin FIG. 10 are NMOS transistors 1008, 1010, 1012, 1014, 1024, and 1018,and PMOS transistors 1022, 1028, 1002, 1004, 1006, and 1016.

FIG. 11 represents a block diagram of pull down circuit 204, showing theinputs in_0 209, in_1 211, in_0_25 213, in_1_25 215, received frommultiplexor circuits 240 and 250. FIG. 11 includes pull down impedancecontrol code bit buffer circuit 1102, slowing rate circuit 1104, andpull down output circuits 1108 and 1106.

FIG. 12 represents a single schematic representing both pull down outputcircuits 1108 and 1106. As shown, each pull down output circuit 1108 and1106 includes parallel pull down circuit 1230, two slew rate controlcapacitor circuits, 1210 and 1250, pull down output element 1208, and apull down driver control circuit 1201. Pull down driver control circuit1201 includes inverting transistor pair 1203, transmission gate 1212,and NMOS transistors 1218 and 1220.

FIG. 13 represents a block diagram of parallel pull down circuit 1230,showing the parallel set of supplemental pull down circuits 1300, andinput signals c<8:1> 1122 and in_1 1204. FIG. 13 also shows the outputOUT 206.

FIG. 14 is a schematic of a representative supplemental pull downcircuit 1300 showing supplemental output element 1408, bit drivercontrol circuit 1440, and bit control circuit 1430. Supplemental outputelement 1408 includes NMOS transistor 1406 and 1407. Bit driver controlcircuit 1440 includes transmission gate 1422, inverting transistor pair1420, and NMOS transistor 1424. Bit control circuit 1430 includestransmission gate 1412, inverting transistor pair 1426, and NMOStransistor 1418.

Referring to FIG. 15, slew rate control circuits 1210 and 1250 in FIG.12 are represented as a single schematic representing both slew ratecontrol circuits. As shown, both slew rate control circuits 1210 and1250 receive signal set cb_s<8:1> 226. FIG. 15 includes a plurality ofgate control PMOS transistors 1500 and a parallel set of NMOS capacitors1510 coupled to the gate control PMOS transistors 1500.

FIG. 16 is a schematic of the slowing rate circuit 1104 of FIG. 11,showing a plurality of NMOS transistors 1610 and transmission gates1600, made up of NMOS transistors 1630 and PMOS transistors 1620.

Overview of Operation of Driver Circuitry

Referring now to FIG. 2, there are functional design differences betweenHSTL driver systems and DTL driver systems. Much of the functioning ofthe HSTL driver described in the above-referenced patent applications issymmetric between pulling high and pulling low. For example, the signalswing is from VSS to VDDO, and signals are launched by the turning on ofthe appropriate output circuit.

In contrast, the design of the DTL type driver system herein describedincludes asymmetry. For example, the signal swing is from VDDO/2 toVDDO, some signals are launched by the turning on of an output, and somesignals are launched by the turning off of an output circuit. Inaddition, when the logic of driver is low, dc-current flows through thepull down circuit 204 of the driving-end and through the pull up circuit202 of the receiving end(s). To accommodate these asymmetries betweenpull up and pull down functions, there are corresponding asymmetries inthe design of the overall driver 110, as described below.

The FIG. 1 driver circuits 110 have an output stage that includes a pullup circuit 202 and a pull down circuit 204, shown in FIG. 2 and theoutputs of these two circuits merge at the overall driver output node206. The static logic-level inputs to two special control pins, up_open208 and down_25 210, determine the output resistance of the driver 110under different operating conditions.

In a “data-driving” mode, i.e. oe 220 is high and sel_data_n 260 is low,the driver output 206 logically responds in non-inverting fashion to thedata 212 input. When data 212 is low, the pull up circuit 202 isdisabled thereby causing a high impedance output; and the pull downcircuit 204 is enabled thereby causing a controlled-resistanceconnection between the output node and the VSS rail. When data 212 ishigh, the opposite occurs with the pull up circuit 202 coupling thedriver output 206 to the VDDO rail through a controlled resistance.

Although the output resistance of the pull up circuit 202, when enabled,is matched to the characteristic impedance of the transmission line(typically 50 Ohms), the output resistance of the pull down circuit 204,when enabled, is a function of the logic-input to control pin down_25210. The output resistance of the pull down circuit 204, when enabled,is 50 Ohms if down_25 210 is low. The output resistance of the pull downcircuit 204 is 25 Ohms if down_25 210 is high. A 25 Ohm pull-downresistance can also be accomplished by having two 50 Ohm pull downcircuits 204 operate in parallel.

In a “data-receiving” mode, the pull down circuit 204 is disabled.However, if the logic-input to the up_open 208 control pin is low, thepull up circuit 202 is enabled and presents a 50 Ohm resistance betweenthe output node 206 and the VDDO rail. If up _open 208 is high, the pullup circuit 202 is also disabled, and the driver 110 presents a highimpedance to the output node 206.

Description of Operation

Referring now to FIG. 2, driver 110 includes various control and datainputs 220 that are logically-converted by control circuit 222, whichmay be represented by an alpha particle radiation-hardenedclock-header/flip-flop cell. Control circuit 222 converts control inputs220, 212, 208 and 210 into logical outputs di_up 214, di_dn 216, anddi25_dn 224.

In one embodiment of the present invention, these three outputs go toinputs of multiplexors 230, 240, and 250. Referring now to FIG. 3, adetailed schematic represents multiplexor 230 in the pull up path, andreferring to FIG. 10, a detailed schematic represents multiplexors 240and 250 in the pull-down path. The logic-level of the sel_data_n 260signal, which is the same signal for each multiplexor, determines whichof the two inputs to each multiplexor 230, 240 and 250, is selected. The“data” input in_d 360, which is a different signal for each multiplexor230, 240, and 250, is selected if sel_data_n 260 is low; and the “test”input in_t 350, is selected otherwise, to determine the givenmultiplexors' outputs.

For example, referring now to FIG. 2 and FIG. 3 in combination, if theselected controlling input (in_d 360 or in_t 350) to multiplexor 230 islow, the output h_or_z_n 203 is high and the output l_or_z_n 205 ishigh-impedance. Conversely, if the controlling input is high, the outputh_or_z_n 203 is high-impedance and the output l_or_z_n 205 is low.

The outputs of multiplexor 230 go to the corresponding inputs of thepull up circuit 202. If input h_or_z_n 203 is high and input l_or_z_n205 is high-impedance, the pull up output elements 508 and 808 will bedisabled and will present a high-impedance to the output node OUT 206.If h_or_z_n 203 is high-impedance and l_or_z_n 205 is low, then pull upoutput elements 508 and 808 (if the corresponding impedance control ishigh) will be enabled and will couple the output node OUT 206 to VDDOthrough a controlled output resistance, as discussed in further detailbelow.

For each of the two multiplexors 240 and 250, if the selectedcontrolling input is low, both of its outputs are high. If thecontrolling input is high, both of its outputs are low.

The two outputs of multiplexor 240, dt_0_n 209 and dt_l_n 211 shown inFIG. 2, provide the in_0 209 and in_l 211 inputs shown in FIG. 11 of thepull down circuit 204, and the two outputs of multiplexor 250, dt_0_25_n213 and dt_l_25_n 215 shown in FIG. 2, provide the in_0_25 213 andin_l_25 215 inputs shown in FIG. 11 of pull down circuit 204. If allfour of these signals are low, the pull down circuit 204 presents ahigh-impedance to the output node OUT 206. If the two outputs from oneof the multiplexors 240 and 250 are high and the two from the other ofthe two multiplexors 240 and 250 are low, then pull down circuit 204will couple the output node, OUT 206, to VSS through a resistance of 50ohms. If all four signals are high, then the pull down circuit 204 willcouple the output node, OUT 206, to VSS through a resistance of 25 ohms.

The mechanisms for controlling output resistance and output slew-rateacross process, voltage and temperature (PVT) variations and across therange of output voltages in both the pull up circuit 202 and the pulldown circuit 204 are described below. These mechanisms for the pull upcircuit 202 depend on the eight-bit codes cbu<8:1> 225 and cbd_s<8:1>226, which are transmitted to the pull up circuit 202. The mechanismsfor the pull down circuit 204 depend on the eight-bit code cbd<8:1> 207which is transmitted to the pull down circuit 204.

Pull up Circuit Path

The elements within multiplexor 230 are shown in FIG. 3. Referring toFIG. 3, the primary control elements include NMOS transistor 302, PMOStransistor 304, PMOS transistor 306, NMOS transistor 308, and NMOStransistor 310. The gates of each of the transistors 302, 304, 306, 308and 310 are controlled via nodes in the sel_data_n 260 path. Whensel_data_n 260 is low, transistors 302, 304, and 308 are enabled andtransistors 306 and 310 are disabled. As a result, when sel_data_n 260is low, outputs h_or z_n 203 and l_or_z_n 205 respond to 312 and 314,which are under the control of input in_d 360. If sel_data_n 260 ishigh, the pattern of enabling and disabling of the multiplexing elementsis reversed. Thus, the outputs respond to PMOS transistor 316 and NMOStransistor 318 which are controlled by node int4 394. Node int4 394 islogically equivalent to input in_t 350 under normal operatingconditions.

The type of multiplexing structure used here readily supports therequisite production of high-impedance outputs. Each output, when nothigh-impedance, need only be pulled towards one of the rails.Single-transistor pass-gates with the appropriate polarity can be usedfor the multiplexing circuits. Accordingly, complementary pairtransistor transmission gates are not necessary. As described more fullybelow, NMOS transistor 302 is shown in parallel with PMOS transistor304, producing an advantageous rate of pulling-up of h_or_z_n 203 thatis advantageous for proper output slew-rate control of the overalldriver 110.

Inverting multiplexor 230 includes fail-safe circuit 390. The fail-safecircuit 390 includes “fail-safe” circuitry that assures that ifcore-power fails while I/O power remains on h_or_z_n 203 will be highand l_or_z_n 205 will be high-impedance. As a result of the fail safecircuit 390, the pull up circuit 202 will present a high-impedance tothe output node OUT 206. The inverter 319 is on core-power, so that itsoutput, seld_n_n 396, will be low if core-power fails. The remaininginverters in the sel_data_n 260 path, i.e. inverter 321 and inverter323, are on I/O power, so they will remain active if I/O power remainson. Consequently, in the event of a core-power failure with I/O powerremaining on, node seld_n 398 will be high and node seld 392 will below, and the outputs of the multiplexing structure will respond to thein_t 350 path rather than the in_d 360 path.

Inverters 320 and 326 on the in_t 350 path are on core-power so thatnode int2 352 and node int4 394 will be low if core-power fails and ifI/O power from source VDDO remains on. The outputs of the multiplexors230 respond to the in_t 350 path, i.e. node 394, if core-power fails andthe I/O power remains on. Thus, h_or_z_n 203 will be high and l_or_z_n205 will be high-impedance.

NMOS transistors 325 and 327 assure that nodes seld_n_n 396 and int2352, respectively, go completely to VSS upon core-power failure when I/Opower is still on. For example, if seld_n_n 396 had been high prior tocore-power failure, inverter 319 would only pull signal seld_n_n 396down to the threshold voltage, V_(th), after the core-power failuresince a PMOS transistor cannot pull a node any lower than V_(th). NMOStransistor 325 thus pulls seld_n_n 396 down further to VSS.

Referring now to FIG. 4, pull up circuit 202, contains an 8-bit buffercell, 410 and a pull up output circuit 420. The buffer cell 410 has twopurposes. First, the buffer cell 410 assures that the impedance-controlbit-code signals are driven with the proper strength. Second, the buffercell 410 does “level-shifting” of the bit-code signals from thecore-power (VDD) domain to the I/O-power (VDDO) domain. As shown in FIG.4 and FIG. 2 in combination, pull up output unit 420 includes logiccontrolled by the outputs of multiplexor 230: the h_or_z_n 203 signal,which is connected to the h_or_z_n 203 pin of multiplexor 230, and thel_or_z_n 205 signal, which is connected to the l_or_z_n 205 pin ofmultiplexor 230. The output resistance and slew-rate of pull up outputcircuit 420 are controlled across PVT variations by the eight-bit codescbu<8:1> 225 and cbd_s<8:1> 226, as described in further detail below.

Referring now to FIG. 5, pull up output circuit 420 is shown in greaterdetail. As shown, pull up output circuit 420 includes inverter cell 510,which is an inverter whose pull-down resistance/strength is controlledacross PVT variations by the eight-bit code cbd_s<8:1> 226. Invertercell 510 accepts the l_or_z_n 205 signal as its input and inverts itslogic-sense to produce output l_or_z 506.

Referring now to FIG. 6 in combination with FIG. 5, inverter cell 510 isshown with greater detail. As shown, there are eight NMOS transistors600, connected in parallel with their common drain 602 connected to thesource of pull-down NMOS transistor 690. Functionally, the larger thenumber of transistors 600 that are enabled by having an enabling gateinput, the smaller the resistance in series with NMOS transistor 690. Asa result, when the l_or_z_n 205 input to inverter cell 510 is high theresistance through which node l_or_z 506 is pulled down is lowered ascbd_s <8:1> 226 has progressively more enabled bits.

Referring back to FIG. 5, when the input to node h_or_z_n 203 ishigh-impedance and the input to node l_or_z_n 205 is low, PMOStransistor 512 and NMOS transistor 514 pull down on node h_or_z_n 203while NMOS transistor 516 pulls up on this node. Because transistor 512is much larger than transistor 516, it will succeed in pulling horzn 203down to a threshold voltage, V_(th), above VSS, at which pointtransistor 512 will become disabled (since its gate-source voltage willno longer exceed V_(th)). As a result, the voltage on h_or_z_n 203 willbe no higher than V_(th). Instead, the voltage on h_or_z_n 203 will bebetween 0 (i.e.VSS) and V_(th) as determined by the outcome of the“drive-fight” between transistors 516 and 514. The resulting voltageoutcome is fairly independent of PVT variations because both transistorsare NMOS transistors, and, therefore, respond similarly to PVTvariations.

The gate of transistor 516 is connected to the output node OUT 260.Thus, the higher the output voltage, the greater the drive-strength oftransistor 516, and the higher the resulting voltage on h_or_z_n 203.The purpose of this feature is to keep the output resistance of the pullup circuit 202 fairly constant across variations in the output voltage,as explained more fully below.

Still referring to FIG. 5, a PFET capacitor, 522, is connected betweenthe output node OUT 206 and h_or_z_n 203 so that the voltage on h_or_z_n203 will respond more quickly to changes in the output voltage than ifsuch response were dependent on the action of transistor 516 alone.

When the input to h_or_z_n 203 is high and the input to l_or_z_n 205 ishigh-impedance, node l_or_z_n 205 is pulled high to VDDO, the voltage onh_or_z_n 203, by transistor 512. Additionally, transistor 514 pulls upon l_or_z_n 205 until its gate-source voltage drops below V_(th), atwhich point it becomes cut-off. When l_or_z_n 205 goes high, l_or_z 506goes low.

The pull up “base-bit” output element 508 is an output element whosefunctioning is independent of the control bits cb <8:1> 424 of the pullup output unit 420. The base bit output element 508 is the parallelcombination of PMOS transistor 526 and NMOS transistor 528. The gate oftransistor 526 is connected directly to signal input h_or_z_n 203.Similarly, the gate of transistor 528 is connected to l_or_z 506. Thus,referring to FIG. 2 in combination with FIG. 5, if the input to h_or_z_n203 from multiplexor 230 is high and the input to l_or_z_n 205 frommultiplexor 230 to pull up circuit 202 is high-impedance, causing nodeh_or_z_n 203 (and l_or_z_n 205) to be high and node l_or_z 506 to below, both transistors of the output element 508 will be disabled andwill present a high-impedance to the output node OUT 206. If the inputfrom multiplexor 230 h_or_z_n 203 is high-impedance and the input frommultiplexor 230 to l_or_z_n 205 is low, then the node h_or_z_n 203 willbe relatively low (the exact level being determined by the drive-fight)and the node l_or_z_n 205 will be low and node l_or_z 506 will be high.Consequently, both transistors of output element 508 will be enabled andwill couple the output node, OUT 206, to VDDO through a controlledoutput resistance. The mechanisms of controlling the output resistanceare described in the further detail below.

Referring now to FIG. 5 in combination with FIG. 7, pull up output unit420, shown in detail in FIG. 5, shows parallel pull up circuit 530.Within parallel pull up circuit 530 there is a set of eight“supplemental pull up bit” cells 700, shown in FIG. 7. Each of thesecells 700 accepts the h_or_z_n 203 and l_or_z 506 signals shown in FIG.5 inputs to parallel pull up circuit 530, and each accepts onecorresponding signal from the set cb<8:1> 424 as an input.

Referring now to FIG. 8, within each of these cells 700 is a pull upoutput element 808 similar to element 508 shown in FIG. 5, consisting ofthe parallel combination of transistors, PMOS transistor 826 and NMOStransistor 828.

Still referring to FIG. 8, when a cell 700's cb<8:1> 424 input is high,bit_ctl_bar 805 is low. As a result, the two transmission gates in thebit control circuit 850 become enabled. The two transmission gatesconsist of transmission gate 820, which includes PMOS transistor 810 andNMOS transistor 812, and transmission gate 830, which includes PMOStransistor 814 and NMOS transistor 816. Enabling transmission gates 820and 830 causes the two transistors of the output element 808 to becontrolled by the h_or_z_n 203 and l_or_z 506 signals. In such case,PMOS transistor 854 and NMOS transistor 852 disable and do not affectthe supplemental pull up circuit 700 functioning. PFET capacitor, 860,similar to PFET capacitor 522, is coupled between the output node OUT206 and h_or_z_n 203 so that the voltage on h_or_z_n 203 will respondmore quickly to changes in the output voltage.

Conversely, when a supplemental pull up circuit 700's cb<8:1> 424 inputis low, node bit_ctl_bar 805 is high. As a result, transmission gates820 and 830 are disabled, so that the two transistors of output element808 are decoupled from the h_or_z_n 203 and l_or_z 506 signals. In suchcase, transistors 854 and 852 are enabled and serve to turn off thetransistors 826 and 828 of output element 808. Thus, this supplementalpull up circuit 700 will present a high impedance to the output node OUT206, regardless of the values of h_or_z_n 203 and l_or_z 506.

Referring back to FIG. 5 in combination with FIG. 9, pull up outputcircuit 420 also contains a set of NMOS capacitors within slew ratecontrol capacitor circuit 550. Slew rate control capacitor circuit 550is shown in detail in FIG. 9. As shown, eight NMOS capacitors 900 areshown, each of which is coupled to the h_or_z_n 203 node in the pull upoutput circuit 420 when the corresponding PFET pass-gate 910 is enabled.The pattern of enabling/disabling of pass-gate transistors 910 iscontrolled by the corresponding bits of code cbu<8:1> 207, which areconnected to the gates of the transistors 910. The resulting pattern ofcoupling/decoupling of the NMOS capacitors 900 with respect to theh_or_z_n 203 node contributes to control of the output slew-rate of thepull up circuit 202, as described more fully below.

Pull Down Circuit Path

Referring now to FIG. 2 in combination with FIG. 10, both pull downmultiplexors 240 and 250 are represented by circuit 1000 as one genericcircuit in FIG. 10. Although FIG. 10 represents a single circuit 1000for both multiplexors, FIG. 2 shows that the difference in themultiplexors 240 and 250 is that multiplexor 240 receives a differentin_t 1020 signal, i.e. ti_dn 228, than multiplexor 250, i.e. ti_dn25232.

The primary multiplexing elements within pull down circuit 204 includetransistors 1002, 1004, 1006, 1016, 1008, 1010, 1012, and 1014, whosegates are under the control of nodes in the sel_data_n 260 path. Whensel_data_n 260 is low, transistors 1002, 1006, 1008, and 1012 areenabled and 1004, 1016, 1010, and 1014 are disabled, causing outputsout_0_n 1050 and out_l_n 1060 to respond to PFET transistor 1022 andNMOS transistor 1024, which are transistors under the control of inputind 1026. If sel_data_n 260 is high, the pattern of enabling anddisabling of the multiplexing elements 1002, 1004, 1006, 1016, 1008,1010, 1012, and 1014 is reversed. Thus, the outputs respond to 1028 and1018 which are controlled by node int4 1030, which is logicallyequivalent to input in_t 1020 under normal operating conditions.

The type of multiplexing structure used for multiplexors 240 and 250advantageously provides output slew-rate control of the overall driver,as explained below. The difference in drive strengths between out_0_n1050 and out_l_n 1060 can produce different slew rates, which cancompensate somewhat for the differences in gate delay among driverelements in pull down circuit 204, i.e. in_0 and in_1 received frommultiplexor 240, and in_0_25 and in_l_25 received from multiplexor 250.

The circuit 1000 includes “fail-safe” circuitry similar to circuit 230,discussed above relative to the pull up path. The fail safe circuitryassures that if core-power fails while I/O power remains on out_0_n 1050and out_l_n 1060 will be low so that the output from the pull downoutput circuit 1108, and similarly 1106, discussed below, will present ahigh-impedance to the output node. Inverter 1070 is on core-power, sothat its output will be low if core-power fails. The remaining invertersin the sel_datan 260 path, i.e. transistor pair inverter 1072 andtransistor pair inverter 1074, are on I/O power. As a result, inverters1072 and 1074 remain active if I/O power remains on. Consequently, nodeseld_n 1080 will be high and node seld 1082 will be low, resulting inthe outputs of the circuit 1000 responding to the in_t 1020 path ratherthan the in_d 1026 path.

Additional fail safe circuitry includes inverter 1084 and inverter 1086,both of which are coupled to in_l 1020. Inverter 1084 is on core-powerso that node in1n 1085 will be low and node int4 1030 will be high, ifcore-power fails and I/O power remains on. Thus, under fail safeconditions, the outputs of the circuit 1000 respond to the in_t 1020path, (i.e. int4 1030) and out_0_n 1050 and out_l_n 1060 present a lowsignal.

NMOS transistors 1090 and 1092 assure that nodes seld_n_n 1071 and intln1085, respectively, reach VSS upon core-power failure when I/O power isstill on. For example, if seld_n_n 1071 is high prior to core-powerfailure, inverter 1070 pulls signal seld_n_n 1071 down to V_(th) afterthe core-power failure because a PMOS transistor cannot pull a node anylower than V_(th). Next, transistor 1090 pulls seld_n_n down the rest ofthe way to VSS.

Referring now to FIG. 11, pull down circuit, 204, includes an 8-bit pulldown buffer circuit 1102, two pull down output circuits, 1108 and 1106,and a slowing rate circuit 1104.

Pull down bit buffer circuit 1102 serves two purposes: a) to assure thatthe impedance control bit-code signals cbd<8:1> are driven with theproper strength, and b) to do “level-shifting” of the bit-code signalsfrom the core-power (VDD) domain to the I/O-power (VDDO) domain. Bitbuffer circuit 1102 receives cbd<8:1> 207 and outputs c<8:1> 1122.

Referring to FIG. 10 and FIG. 11 in combination, each pull down outputcircuit 1106 and 1108 includes logic controlled by the outputsgenerically shown as out_0_n 1050 and out_l_n 1060 of multiplexorcircuit 1000, which go to inputs of the pull down output circuits 1106and 1108, in_0 and in_l. As described below, each pull down outputcircuit 1106 and 1108 has an output resistance and slew rate that arecontrolled across PVT variations by the eight-bit codes c<8:1> 1122 andcbd_s<8:1> 226, which are connected to corresponding input pins of thesame name. The slowing rate circuit 1104 accepts the buffered versionsof the eight impedance-control bit-code signals, c<8:1> 1122, andoutputs a logically-identical set of signals, cbd_s<8:1> 226, with ratesof transition in the outputs that are slower than the rates for theinputs, particularly for high-to-low transitions. Accordingly, theslowing rate circuit 1104 reduces the amplitudes of transitory “spikes”in the driver output OUT 206, that can occur if such transitions occurtoo quickly.

Referring now to FIG. 12, the pull down output circuits 1106 and 1108are represented by one circuit 1200. Pull down output circuits 1106 and1108 are different only in the signals in_0 1202 and in_l 1204 input tothe pull down output circuits 1106 and 1108. As shown in FIG. 11, pulldown output circuit 1108 receives signals in_0 209 and in_l 211, andpull down output circuit 1106 receives signals in_0_25 213 and in_l_25215. For purposes of simplification, signals 209, 211, 213, and 215 arerepresented in FIG. 12 as signal in_0 1202 and signal in_l 1204.

Referring back to FIG. 12, pull down base bit output element 1208includes a parallel combination of two NMOS transistors, 1206 and 1207.Input in_0 1202 is coupled directly to the gate of 1206, therebydirectly controlling whether transistor 1206 is enabled or disabled.Input in_0 1202 also controls whether or not NMOS 1214 of transmissiongate 1212 is on or off. The logic-level of input in_l 204 controls theenabling/disabling of PFET 1216 of transmission gate 1212. Additionally,the logic-level of input in_l 1204 controls whether NMOS transistor 1218is on or off. NMOS transistor 1220 is in series with transistor 1218 andis always enabled, serving to limit the current through transistor 1218,thereby controlling the fall-rate of node gt_pd2 1222 when transistor1218 is enabled.

Signals in_0 1202 and in_l 1204 always have the same logic-level andslightly different transition rates. As a result, if in_0 1202 and in11204 are high: 1) transistor 1206 is turned on directly, 2) transistor1218 is off, and 3) transmission gate 1212 is enabled, thereby couplingthe gate of transistor 1207 to the output node OUT 206. Because thegate-source voltage of transistor 1207 is a function of theoutput-voltage OUT 206, transistor 1207 may be cut-off even iftransmission gate 1212 is enabled.

Further, if in_0 1202 and in_l 1204 are low: 1) transistor 1206 isturned off directly and 2) transistor 1207 is turned off sincetransmission gate 1212 is disabled and transistor 1218 is enabled sothat transistor 1218 pulls down the gate of transistor 1207. In summary,if in_0 1202 and in_l 204 are high, pull down output element 1208 willcouple the output node OUT 206 to the VSS rail through a finiteresistance. Conversely, if in_0 1202 and in_l 1204 are low, pull downoutput element 1208 will present a high-impedance to the output node OUT206. The in_l204 signal also goes to the input of parallel bit circuit1230, shown in further detail in FIG. 13.

Referring now to FIG. 13, eight supplemental pull down circuits, 1300connected in parallel are shown within parallel bit circuit 1230.Referring to FIG. 13 in combination with FIG. 14, one of the pluralityof supplemental pull down circuits 1300 is shown in greater detail inFIG. 14. As shown in FIG. 14, each supplemental pull down circuit 1300receives one of the impedance control bit signals cb<8:1> 1122. Further,each supplemental pull down circuit 1300 includes a supplemental pulldown output element 1408 similar to the pull down output element 1208located in the pull down output circuit 1200.

Functionally, when the corresponding impedance control bit input cb<8:1>1122 input is high, transmission gate 1412, which includes NMOStransistor 1409 and PMOS transistor 1404 becomes enabled and NMOStransistor 1418 becomes disabled. In such case, the enabling anddisabling of the pull down output element 1408 is controlled by the in1204 input in the same manner as in the base bit pull down element 1208shown in FIG. 12. When the bit of cb<8:1> 1122 is low, transmission gate1412 becomes disabled, decoupling output element 1408 from the in 1204input. NMOS transistor 1418 becomes enabled, causing output element 1408to become disabled.

Accordingly, output element 1408 in each supplemental pull down circuit1300 will be disabled when: 1) the appropriate bit of cb<8:1> 1122 islow, or 2) the appropriate bit of cb<8:1> 1122 is high while in 1204 islow. Conversely, if the ppropriate bit of cb<8:1> 1122 is high while in1204 is high, output element 1408 becomes active. Those supplementalpull down circuits 1300 whose output elements 1408 are enabled presentresistive coupling between the pull down circuit 204's output node andthe VSS rail in parallel with the pull down base bit output element1208. Those with disabled output elements 1408 present high-impedanceoutputs to the pull down circuit 204's output node.

Additionally, within the pull down output circuit 1200, the in_0 1202node connects to the in input of slew rate control capacitor circuit1210, and the in_l 204 node connects to the in input of slew ratecontrol capacitor circuit 1250.

Referring now to FIG. 15, both slew rate control capacitor circuits 1210and 1250 are shown in further detail. As shown, both slew rate controlcapacitor circuits 1210 and 1250 contain a set of eight NMOS capacitors1510. Each NMOS capacitor 1510 has a corresponding PFET transistorpass-gate 1500 connected between the gate of the respective NMOScapacitor 1510 and the capacitor circuit in 1520 node. The gates of eachPFET transistor 1500 is coupled to a corresponding bit among cb_s<8:1>226. When the input bit received by the PFET transistor 1500 gate islow, the respective PFET transistor 1500 is on and the gate of thecorresponding NMOS capacitor 1510 is coupled to node in 1520. If thegate input to the PFET transistor 1500 gate is high, the PFET transistor1500 is off and the NMOS capacitor 1510 is decoupled from node in 1520.The sets of capacitors shown in FIG. 15 contribute to control of theoutput slew-rate of the pull down circuit 204, further described below.

Referring now to FIG. 11 in combination with FIG. 16, slowing ratecircuit 1104 is shown in further detail. As shown, slowing rate circuitreceives in<8:1> 1122 from bit buffer circuit 1102 and outputs cb_s<8:1>226. Functionally, slowing rate circuit 1104 limits the rate at whichthe cb_s<8:1> 226 signals can switch, particularly the high-to-lowtransitions. Limiting the rate of signal switching limits the amplitudesof “tugs” on the in_0 and in_l nodes 1130, 1132, 1134, and 1136 in pulldown output circuits 1108 and 1106. Such “tugs” are due to: 1)“charge-sharing” between the in_x nodes and the gates of thecorresponding NMOS capacitors 1570 within 1210 or 1250 if the in_x nodes1130, 1132, 1134, and 1136 are at different voltages than thecapacitor-gates prior to their being coupled, and 2) Miller-capacitivecoupling (via the gate-source capacitance of the PFET pass-gates)between the cb_s<8:1> 226 signals and the in_x nodes 1130, 1132, 1134,and 1136. The “charge-sharing” tug occurs on high-to-low transitionsonly, while Miller-capacitive tugs occur for both transitions. Such tugscan produce brief changes in the gate-voltages of output-element 1208transistors 1207 and 1206, and of output element 1408 transistors 1407and 1406 for enabled elements 1300, thereby producing brief changes inthe output-resistance of the pull down circuit 204. The brief changes,in turn, can produce undesirable voltage-spike “glitches” in the outputof the driver 110. Keeping the transition rate of the cb_s<8:1> 226signals slow keeps the amplitudes of the tugs small, whichadvantageously limits the amplitudes of the out put voltage-spikeglitches.

Referring to FIG. 16, each path from an in <8:1> 1122 node to itscorresponding cb_s<8:1> 226 node in the slowing rate circuit 1104 goesthrough a parallel combination of a diode-connected NMOS transistor 1610and a transmission gate 1600. PFET transistor 1620 of each transmissiongate 1600 is sized to have a small enough channel length and a largeenough width so that low-to-high transitions are only slightly slowed atthe output cb_s<8:1> 226 compared to the input 1122, but are slowed tolimit output-glitches due to Miller-capacitive coupling to tolerablelevels.

Because high-to-low tranitions at the output cb_s<8:1> 226 produce bothtypes of tugs, and the “charge-sharing” tug can be particularly large ifthe transition rate is too fast, the rate of the high-to-low transitionsat the output cb_s<8:1> 226 must be significantly slower than thelow-to-high transitions (which only produce Miller-capacitive tugs) toprevent intolerable output-glitch amplitudes. Therefore, each NMOStransistor 1630 in each transmission gate 1600 is very resistive, havinga large channel length and a small channel width. Although each PFETtransistor 1620 in each transmission gate 1600 contributes to the earlypart of the high-to-low transition, each PFET transistor 1620 becomes“cut-off” when the output voltage at node cb_s<8:1> 226 drops belowV_(th). As a result, the early part of the high to low transition isrelatively fast, while the latter part is relatively slow. The speed ofthe early part of the transition produces little “charge-sharing” tugbecause the PFET transistors 1500, shown in FIG. 15 do not turn on untiltheir gate-voltage (i.e. the output of slowing rate circuit 1104) fallsat least V_(th) below VDDO. The diode-connected NMOS transistors 1610also contribute to the early part of the high-to-low transition to keepthe transition from being impractically slow (a particular risk in slowp-process PVT corners), but it also cuts off when the output voltage atnode cb_s<8:1> 226 drops below V_(th). Once transistors 1610 and 1620are cut off, the only highly resistive 1630 transistors contribute tothe high to low transitions. Because transistors 1630 are so resistive,the latter part of the high to low transition is very slow. Therefore,the full turning on of PFET's 1500 is very slow. Consequently, thecharge-sharing tug is spread widely over time, limiting the amplitude ofany resulting output voltage glitches on the output of pull down circuit204.

Output Impedance Matching and Linearization

Referring now to FIG. 4 and FIG. 11, two output impedances thatcharacterize the pull up output circuit 420 and the pull down outputcircuits 1108 and 1106 include a “dc” impedance and an “ac” or“instantaneous” impedance. As one skilled in the art appreciates, the dcoutput impedance at a given output voltage is given by the drain-sourcevoltage, V_(DS), divided by the drain-source (output) current, I_(DS).Graphically, this corresponds to the inverse of the slope of a line fromthe origin to the point on the unit's I_(DS) vs. V_(DS) curvecorresponding to the given voltage. The ac output impedance at a givenvoltage is given primarily by the inverse of the instantaneous slope ofthe I_(DS) vs. V_(DS) curve of the unit at the given voltage, but it isalso affected by the capacitances and other “parasitics” loading theoutput node OUT 206.

The value of the dc output impedance affects a) the value of the voltageat the driver end upon launching a signal, b) the value of the voltageat the bus-node during intermediate (but sustained) states before thebus eventually settles, and c) the final value of the voltage to whichthe bus settles. For two-node DTL type systems in particular, it isimportant that the voltage at the receiving end of a launched signalsettle to the final value upon the arrival of the incident wave.Further, in a back-to-back low-to-low signal switch, both ends launchsignals simultaneously. Proper signal settling requires that the pull upcircuit 202 and the pull down circuit 204 dc-impedances equal thecharacteristic impedance of the transmission line (e.g. 50 ohms).Because the bus voltage will be VDDO/2 under such circumstances, the dcoutput impedance of each of the pull up driver output units must bedesigned to be about 50 ohms when the voltage at its output node isVDDO/2. More specifically, the dc-impedance of the pull up circuit 202is designed to be slightly more than 50 ohms, and the dc-impedance ofthe pull down circuit 204 is designed to be slightly less than 50 ohmsresulting in an output swing will always be at least VDDO/2.

The ac output impedance constitutes the impedance “seen”. by a signaledge as it impinges on a driver-output node. If the ac output impedanceis designed to match that of the transmission line, wave fronts arrivingat the driver terminate cleanly. If not, there will be “reflections” ofthe signal edge that propagate back into the transmission line.Reflections may increase the time required for the voltage on the lineto settle to a level recognizable as having a high or low digital sense,thereby lowering the attainable signaling frequency. Maintaining aconstant ac impedance is facilitated by maintaining a constantinstantaneous slope of the I_(DS) vs. V_(DS) curve for the output unitover the range of output voltages.

For drivers consisting of transistors, establishing and maintaining adesired output impedance is problematic. The impedance characteristicsof a transistor vary with process, supply voltage, and temperature (PVT)and with changes in the voltages across the terminals of the transistor.Special circuit schemes are needed to compensate for these variations.

Controlling Impedance across PVT Variations, Pull up circuit

Referring now to FIG. 4, FIG. 5, FIG. 6 and FIG. 8 the pull up outputcircuit 420 includes a parallel combination of nine pull up elements.The nine pull up elements include the base bit pull up output element508 which is always enabled to respond to the signals on inputs h_or_z_n203 and l_or_z_n 205, and eight supplemental output elements 808 whichare selectively enabled and disabled by the eight bit code cbu<8:1> 225to compensate for dc-impedance variations due to PVT variations. Eachpull up output element 508 and 808 consists of a PMOS transistor, 526and 826, respectively, and an NMOS transistor, 528 and 828 respectively,connected in parallel. One end of the parallel combination is coupled toVDDO and the other to the output node of the driver OUT 206.

As described above, proper swing of the output voltage requires that thedc output impedance be kept near a certain value (i.e. 50 ohms) when theoutput voltage is near VDDO/2. In the fastest PVT corner, only the basebit is enabled. Therefore, the pull up output element 508 transistors inthe base bit are sized so that the dc-impedance of their parallelcombination is close to 50 ohms in the fastest corner when the outputvoltage equals VDDO/2. In the supplemental pull up circuits 700, thesupplemental output element circuits 808, with the equivalent twotransistors 826 and 828, are sized so that the enabling of each bit in apredetermined sequence reduces the prevailing net impedance by a fixedpercentage (approximately 7% for this embodiment only). By enabling anddisabling the proper number of bits, the dc-impedance of pull up circuit202, when the output voltage equals approximately VDDO/2, can be set tobe within a fixed percentage (approximately 7% for this embodiment only)of the desired level (e.g. 50 ohms) in all of the PVT corners.

Controlling Impedance across Variations in OutVut Voltage, Pull upcircuit

Referring back to FIG. 5 and FIG. 8 in combination with FIG. 2, as theoutput voltage at node OUT 206 varies, there are changes in the voltagesacross the terminals of each transistor in pull up circuit 202 that iscoupled to the output node OUT 206. The transistors coupled to theoutput node OUT 206 include the transistors in output elements 508 and808. The changes in voltages across the transistors changes the output(drain-source) current of each transistor in output elements 508 and808. For each individual transistor in elements 508 and 808, therelationship between its drain-source current, I_(DS) and itsdrain-source voltage, V_(DS), (i.e. its output resistance) changes overthe range of possible output voltages. However, the net output currentof each the output element 508 and 808 is the sum of the drain-sourcecurrents of the transistors in the given output element, i.e.,transistors 526 and 528 in output element 508, and transistors 826 and828 in output element 808. Further, the net output resistance of eachoutput element 508 and 808 is that of the parallel combination of theoutput resistances of the appropriate pair of transistors. Therefore, ifthe output currents and output resistances of the two output transistorsin output elements 508 and 808 can be designed to change in acomplementary manner as the output voltage varies, the net outputresistance of the overall pull up circuit 202 can be kept fairlyconstant as the output voltage varies.

Referring now to FIG. 5 and FIG. 8, transistors 526 and 826 are“normally-connected” in the sense that there source nodes are coupled tothe rail VDDO, and their drain nodes are connected to the output node,OUT 206, and their gate nodes are not coupled directly to the outputnode 206 when the transistors are active. Consequently, the I_(DS) vs.V_(DS) relationship for these transistors 526 and 826 generally movesalong a characteristic curve. However, the gate-voltage of thetransistors 526 and 826 is not fixed, but increases as the outputvoltage increases. This is because the gate voltage is generated by theoutcome of the “drive-fight” between transistors 516, 514 and 512. Thehigher the output voltage at node OUT 206, the stronger the sourcefollower transistor 516, and the higher the gate-voltage on transistor526 and 826.

Therefore, at any given output voltage (i.e. VDDO−V_(DS)), theparticular characteristic curve governing the I_(DS) vs. V_(DS)relationship for transistors 526 and 826 is also a function of the valueof the output voltage. As the output voltage increases, the gate-voltageincreases and, therefore, the gate-source voltage decreases, therebyselecting a characteristic curve with a lower I_(DS) for a given V_(DS).The net result is an I_(DS) vs. V_(DS) relationship that is more linearthan it is for a normal characteristic curve as shown in FIG. 17. Thisis particularly so at lower V_(DS) values (i.e. output voltage valuesbetween VDDO/2 and VDDO), which is the normal operating range for pullup circuit 202.

The NMOS transistors in each pull up output element, 528 and 828 are“diode-connected”, meaning the gate nodes are at the same voltage as thedrain nodes when active. Consequently, the drain-source voltage isidentical to the gate-source voltage and, therefore, always greater thanthe difference between the gate-source voltage and the thresholdvoltage,(V_(DS)>V_(GS)−V_(t)). Thus, each 528 and 828 transistoroperates in its saturation region until the output voltage rises towithin a threshold voltage of VDDO, at which point each 528 and 828transistor is “cut off”. The gate-source and drain-source voltages varysimultaneously, and the output current is a function of each. However,the effects of changing the gate-source voltage of each 528 and 828transistor dominates, so that the shape of its I_(DS) vs. V_(out) curveis similar to that of its transconductance curve. This curve is nearlylinear when the gate-source voltage exceeds the threshold voltage (e.g.when the output voltage is more than a threshold voltage below VDDO).

The net I_(DS) vs. V_(out) curve for the pull up circuit is the parallelcombination of those for transistors 526 and 528 in output element 508,and transistors 826 and 828 in output element 808. Thus, with properrelative sizing of the transistors in pull up output elements 508 and808, and the “drive-fight transistors” 516, 514 and 512, the net I_(DS)vs. V_(out) curve for the pull up circuit 202 can be kept fairly linear,constituting a constant ac impedance, over the range of possible outputvoltages. Of particular interest is the range of output voltages betweenVDDO/2 and VDDO, the normal operating range for the pull up circuit 202.In this range, the contribution from NMOS transistors 528 and 828 isvery small relative to that of PMOS transistors 526 and 826. Therefore,the slope of the net I_(DS) vs. V_(out) curve is dominated by that forPMOS transistors 526 and 826, and the “drive-fight” mechanism describedabove has made this curve very linear in this range of output voltagesas shown in FIG. 17.

Controlling Impedance across PVT Variations. Pull down circuit

Referring now to FIGS. 11, 12 and 14, in combination with FIG. 2,impedance matching across PVT variations is accomplished in the pulldown output circuit 1106 and 1108 in the same manner as in pull upcircuit 202. For each pull down output circuit 1106 and 1108, there arenine pull-down output elements 1208 and 1408, pull down output element1208 in the base bit circuit 1200, and supplemental pull down outputelement 1408 in the supplemental pull down circuits 1300. In each pulldown output circuit 1106 and 1108, the pull down output elements 1208and 1408 are connected in parallel between the output node OUT 206 andVSSO. The base bit pull down output element 1208 is always enabled, andthe supplemental output elements 1408 are selectively enabled anddisabled by the eight bit code cbd<8:1> 207 to give the desired dcimpedance when the output voltage equals VDDO/2.

Controlling Impedance across Variations in Output Voltage, Pull downcircuit

Referring to FIG. 14 and FIG. 12 in combination, pull down outputelements 1208 and 1408 provide linearization of the pull down impedanceacross variations in the output voltage. Each pull down output element1208 and 1408 consists of two NMOS transistors, transistors 1206 and1207 in pull down output element 1208, and transistors 1406 and 1407 inpull down output element 1408. Each of the transistor pairs areconnected in parallel and have output currents and output impedancesthat change in complementary manners as the output voltage at node OUT206 changes. Consequently, with proper channel sizing, the net dc and acimpedance of the parallel combination stays nearly constant near thedesired value (e.g. 50 ohms) over most of the range of output voltages.

Although each bit of the pull up circuit 202 achieves impedancelinearization by connecting a PFET transistor in parallel with an NMOStransistor, it would be impractical to use a P channel device in theoutput element of the pull down circuit 204 as the width of the Pchannel device would have to be very large. Accordingly, pull downcircuit 204 connects two NMOS transistors in parallel for each bitoutput element of the pull down circuit 204. For example, in the basebit circuit 1200, NMOS transistors 1206 and 1207, together outputelement 1208, are connected in parallel. When the pull down outputelement 1208 is active, the transistor 1206 is connected in the “normal”manner for an NMOS pull down transistor, and 1207 is “diode-connected”via transmission gate 1212.

As a result, when pull down output element 1208 is active, transistor1206 operates in the saturation region, and acts as a nearly-constantcurrent source when the output voltage is less than a threshold voltagebelow VDDO. When the output voltage is below that, transistor 1206operates in its “linear” region. When the output voltage is more than athreshold voltage above VSS, transistor 1207 operates in the saturationregion; otherwise transistor 1207 is “cut off”.

The output current of transistor 1206 follows its characteristic curveas the output voltage varies, and the output current of transistor 1207generally follows the transconductance curve. Proper relative sizing ofthe two transistors 1206 and 1207 and proper relative timing of theiractivation can produce a fairly linear relationship, equivalent to thedesired impedance, between the pull down circuit 204 net output currentand the output voltage over most of the output swing. When transistor1207 is cut off, this relationship is controlled entirely by the“linear” region of the characteristic curve of transistor 1206.

Both of the two transmission gate transistors, NMOS transistor 1214 andPMOS transistor 1216 in the base bit pull down output circuit 1200 andNMOS 1414 and 1416 in the supplemental pull down circuit 1300, in eachpull down output circuit 1106 and 1108 are necessary since they havedifferent roles relative to the timing of the activation of transistors1207 and 1406, respectively. As the node in_0 1202 goes high, 1214 turnson, which pulls up the gate of 1207. This allows the activation of 1207to be nearly simultaneous with that of transistor 1206. The activationof 1216 is delayed by an inverter, so that 1214 bears the full burden ofactivating 1207 early in the transition. Because NMOS transistor 1214 iscascode connected, the gate-source voltage falls as the output voltageincreases causing its drive-strength to decrease. By the time theseeffects start to become significant, 1216 has become active and can pullthe gate of 1207 the rest of the way up to the level of the outputvoltage.

Control of Slew Rate

Controlling the driver's output slew rate is needed for severalpurposes, including: a) to limit the amount of “bounce” in signal,power, and ground lines due to rapid current changes (large “di/dt”)interacting with parasitics, b) to control the fraction of thecycle-period consumed by the signal's rise and fall times (as persystem-specifications), and c) to control the amount “crowbar” currentby controlling the lengths of the periods during which the pull upcircuit 202 and the pull down circuit 204 of driver I110 aresimultaneously active. Output slew rate is determined primarily by theoutput impedance of the driver 110 and the rates at which each outputcircuit is enabled and disabled. Strategies for controlling the outputimpedance have been described earlier. Additionally, controlling theslew rates of the voltages on the gates of the output transistorelements 508, 808, 1208 and 1408 control the rates of enabling anddisabling of the pull up and pull down output circuits 420, 1106 and1108.

To achieve the slew rate control goals, the primary step is to establisha desired overall slew rate for the output transistor gate nodes byestablishing an appropriate “RC” constant for the voltage-transition ofthese nodes. More specifically, the product of the output resistance ofthe elements driving a given node and the capacitance loading that nodeis established to produce the desired overall slew rate. According to anembodiment of the present invention, the resulting RC product ismaintained across PVT variations.

Additionally, the peak “di/dt” is controlled to limit “bounce” on therails and signal lines in part by controlling the overall rate oftransition of the gate-nodes, as described above. However, for any givenoverall transition period, the peak “di/dt” will be least if the rampingof the current is linear in time as shown in FIG. 18. Therefore, inaccordance with an embodiment of the present invention, ramping of thecurrent with respect to time is linear.

To maintain a fairly constant output resistance while driver 110switches from pulling high to pulling low (or vice-versa), the enablingof the pull up output circuit 420 and the pull down output circuits 1106and 1108 overlaps for some period of time. The crowbar current createdby the enabling of circuits 420, 1106 and 1108 contributes to thelinearization of the ramping of the currents described above.

Turning-Off of the Pull-Up Output Unit

Turning off the pull up output elements 508 and 808 launches a signaledge if on the previous cycle driver 110 acted as a pull up terminator,and another driver in the system was pulling low. In such a case,current that was flowing from the VDDO-rail through the pull up outputelements 508 and 808 becomes cut-off by the turning off of the pull upoutput circuit 420. Turning off the pull up output circuit 420 launchesa low-going signal edge with a slew rate that must be controlled to meettiming specifications. Additionally, turning off the pull up outputcircuit 420 produces a current change with a rate (di/dt) that must becontrolled to limit rail-bounce. If no other driver in the system pulledthe current down on the previous cycle, then no current was flowingthrough the pull up output circuit 420. In such case, turning off thepull up output circuit 420 does not launch a signal edge or cause achange in current. Additionally, the turning off of the pull up circuit202 is nearly always accompanied by the turning on of the driver's pulldown circuit 204. Therefore, controlling crowbar current is also aconsideration.

Controlling the slew rate of the signal edge at the output node of thepull up output circuit 420 and controlling the rate of current change isaccomplished by controlling the slew rates of the voltages on the gatesof the output element 508 transistors, transistors 526 and 528. For thetuning off of output elements 508 and 808 of the pull up circuit 202,this means controlling the rise-rate of node h_or_z_n 203 and thefallgate of node l_or_z 506. Additionally, for h_or_z_n 203 to risecompletely, l_or_z_n 205 must also be pulled up via PFET transistor 512,mainly; the input to l_or_z_n 205 in such case is high-impedance.

These gate-node transition-rates are controlled mainly by controllingthe “RC-constant” for these transitions, including compensation schemesto keep these RC-values fairly constant across variations in PVTconditions. As PVT variations cause the net output resistance of theelements pulling-up on node h_or_z_n 203 to change, compensatingadjustments to the capacitance loading this node are made. As PVTvariations change the output resistance of the individual elementspulling down on node l_or_z 506 (and the capacitive loading of this nodeby supplemental circuits also changes), the number of the elementsoperating in parallel to pull down node l_or_z 506 is adjusted tocompensate.

Referring to FIGS. 2 and 3 in combination, in data-driving mode, theh_or_z_n 203 node is pulled up by the output path of the pull upmultiplexor 230 consisting of PFET transistor 312 in series with theparallel combination of PFET transistor 304 and NMOS transistor 302. Thepull up impedance-code cbu<8:1> 225 mainly tracks the changes in outputresistance of PFET elements due to PVT variations. The PFET elementstracked include PFET transistors 526 and 826 because currents throughpull up output elements 508 and 808 are dominated by those of therelevant PFET transistor. The pull up impedance-code cbu<8:1> 225 alsolargely tracks the effects of supply-voltage and temperature variationson NMOS transistors, including 828 and 528 but not process variations.Thus, the pull up impedance-code cbu<8:1> 225 accounts for most, but notall, of the resistance variations in NMOS transistor 302 due to PVTvariations. As a result, code 225 can be used to selectively add orremove capacitive loading on node h_or_z_n 203 to compensate fordecreases or increases, respectively, in the output-resistance of theelements that pull up node h_or_z_n 203.

Referring now to FIG. 5, compensation capacitors are contained in pullup capacitor circuit 550, shown in further detail in FIG. 9. Each NMOScapacitor 900 can be coupled to node h_or_z_n 203 by a correspondingpass-gate PMOS transistor 910, the gate of each being driven by acorresponding bit of the pull up impedance control-code cb<8:1> 424. In“faster” PVT corners, in which the output-resistance of the elementspulling-up on h_or_z_n 203 is relatively small, more bits of cb<8:1> 424will be low, enabling more of the pass-gate transistors 910 therebyincreasing the capacitive loading on h_or_z_n 203. In “slower” PVTcorners, the opposite occurs. As a result, as the “R” driving nodeh_or_z_n 203 decreases, the “C” loading node h_or_z_n 203 increases,keeping the “RC” constant for the rise-transition of node h_or_z_n 203fairly constant across PVT variations.

The selective capacitive loading of node h_or_z_n 203 by the capacitorswithin capacitor circuit 550 must also compensate for the variations incapacitive loading on node h_or_z_n 203 due to the enabling anddisabling of the supplemental pull up bit cells 700. For each enabledbit, wherein the corresponding bit of cb<8:1 > 424 is high, thetransmission gate 820 consisting of PMOS transistor 810 and NMOStransistor 812 is enabled so that node h_or_z_n 203 is loaded by thegate-capacitances of PFET capacitors 860 and 826. In each disabledsupplemental bit cell 700 the transmission gate 820 is disabled, so thecorresponding gate capacitance of transistor 860 and 826, is decoupledfrom node h_or_z_n 203. As a result, the capacitance within capacitorcircuit 550 coupled to node h_or_z_n 203 due to a bit of cb<8:1> 424being low must also compensate for the absence of this gate capacitancein the corresponding disabled supplemental bit cell 700.

Referring now to FIG. 5 in combination with FIG. 2 control across PVTvariations of the rate of pulling-down of node l_or_z 506 isaccomplished by utilizing the pull down impedance control code,cbd_s<8:1> 226. Code cb_s<8:1> 226 tracks variations in outputresistance of NMOS transistors across PVT corners. Referring now to FIG.5 and FIG. 6 in combination, in slower PVT corners, the code cb_s<8:1>226 has more high bits, which enables more of the NMOS transistors 600within inverting buffer circuit 510. Thus, as the output resistance ofindividual NMOS transistors 600 increases, the number of transistors inparallel pulling down on node l_or_z 506 is increased to compensate. Asa result, as supplementary bit cells 700 are enabled and disabled thereis control of the enabling of transistors 600 acting as pull downtransistors that also compensates for the variations in capacitiveloading of node l_or_z 506. Although the impedance control code cb<8:1>424 is used for the enabling and disabling of the supplementary bitcells 700, the pull-down code cbd<8:1> 207 tracks code 424 to asignificant degree because responses to voltage and temperaturevariations are fairly common between the two codes. Further, thefraction of pull up output current flowing through NMOS transistor 528is very small, on the order of five percent. Thus, tight control of theslew-rate of transistor 528 is not crucial to proper overallperformance.

Turning-On of the Pull up circuit

In general, in DTL systems, the turning-on of a pull up circuit issometimes a partial contributor, but never the main contributor, to asignal swing. If the turning-on of the pull up of a driver is coincidentwith the turning-off of the pull-down of the same driver, it is thelatter event which dominates the generation of the form of the signaledge. Therefore, the turning-on of pull up circuit 202 primarily servesto limit the size of the resultant overshoot of the voltage at theoutput node to a level that avoids degrading the physical integrity ofthe output transistors 508 and 808. For example, the turning on of pullup circuit 202 limits the overshoot of the voltage at the output node to1.25*VDDO, as opposed to 1.50*VDDO if pull up circuit 202 does not turnon.

The requirements for the slew-rate of the turning-on of the pull upcircuit 202 are relatively limited. The requirements for the slew rateinclude a) the slew rate must be appropriate for allowing the properamount of crowbar current due to overlap with the turning-off of pulldown circuit 204, and b) the slew rate must be fast enough in every PVTcorner to prevent excessive overshoot of the voltage at the output node.

Referring to FIG. 5, the tuning on of the pull up circuit 202 involvesthe pulling down of node h_or_z_n 203 and the pulling-up of node l_or_z506. A major contributor to the pulling down of node h_or_z_n 203 isPFET transistor 512. As described above, the pull up impedance controlcode cb<8:1> 424 is used to control the capacitive loading of nodeh_or_z_n 203 by the capacitors in capacitor circuit 550 so as tocompensate for changes in output resistance of PFET transistors,including PFET transistors 512. Additionally, referring to FIG. 2 andFIG. 3 in combination, code cb<8:1> 424 tracks voltage and temperaturechanges that also affect NMOS transistors, such as 308 and 310 whichpull down on node h_or_z_n 203.

Referring back to FIG. 5, the slew-rate of the pulling-up of node l_or_z506 is not well-controlled across PVT corners. However, NMOS transistor528 contributes only about five percent of the pull up output current atnode 520, so the contribution of this transistor to the transition issmall. Thus, the lack of tight control has little effect on overalldriver 110 functioning.

Turning-Off of the Pull down circuit

In DTL systems, turning off the pull down circuit 204 always launches asignal edge. Referring to FIG. 1, whenever one driver 110 is pullingdown, there is some other driver pulling up. Thus, the current flowsthrough a pull down circuit 204 whenever active. The cutting off of thecurrent flow through the pull down circuit 204 launches a signal.

Referring to FIGS. 2 and 11, the outputs of multiplexor 240 drive theinput nodes in_0 209 and in_l 211 going to pull down output unit 1108.Similarly, the outputs of multiplexor 250 drive the input node in_0_25213 and in_l_25 215 going to pull down output unit 1106. Each systemconsisting of a multiplexor and a pull down input circuit can berepresented by the circuit in FIG. 10 and 12 where the output of FIG. 10is coupled to the input of FIG. 12. Thus, in_0 1202 and out_0_n 1050 arecoupled together and in_l 1204 and out_l_n 1060 are coupled together.

Referring to FIG. 2 in combination with FIG. 10, the slew rate for theturning off of the pull down circuit 204 is controlled by controllingthe slew rate of the pulling down of nodes in_0 209 in_l 211, in_0_25213 and in_l_25 215. FIG. 10 shows a general multiplexor representingboth multiplexors 240 and 250. Nodes in_0 209, in_l 211, in_0_25 213 andin_l_25 215 are referred to jointly herein after with node out_0_n 1050and out_l_n 1060 in FIG. 10. Nodes in_0 209 and in_l 211 are pulled downby the NMOS transistors 1008, 1010, 1024, 1018, 1012 and 1014 of thecircuit shown in FIG. 10. As PVT conditions change, the net outputresistance of NMOS transistors 1008, 1010, 1024, 1018, 1012 and 1014changes. The pull down impedance control code 207 tracks these changesbecause the output pull-down element 1208 consists of NMOS transistors.Therefore, the code 207 can be used to selectively increase or decreasethe capacitive load on node in_0 209 and in_l 211, so that the “RCvalue” for the pulling down of each of these nodes remains fairlyconstant across PVT variations.

Referring to FIGS. 10, 11 and 12, the outputs, out_0_n 1050 and out_l_n1060, are generalized representations of the inputs shown in FIG. 11,i.e., in_0 209, in_l 211, in_0_25 213, and in_l_25 215. As shown in FIG.1, the first two inputs are coupled to pull down output circuit 1108,and the second set of inputs are coupled to pull down output circuit1106. FIG. 12 shows a generic pull down output circuit 1200,representing both pull down output circuits 1108 and 1106. Accordingly,the four inputs discussed above are generically represented in FIG. 12by inputs in_0 1202 and in_l 1204.

Referring to FIG. 11, 12 and 15, bit code 207, shown in FIG. 11, passesthrough slowing rate circuit 1104 and bit buffer circuit 1102, andbecomes code cbd s<8:1> 226. This code 226 is used in pull downcapacitor circuits 1210 and 1250 to control the number of NMOS loadcapacitors 1510 that are connected to their respective input nodes. Nodein_0 1202 is connected to the input of capacitor circuit 1210. As pulldown NMOS PVT conditions become “slower”, the number of control bits incode 226 that are high increases, which reduces the number of capacitorsin capacitor circuit 1210 that are connected to in_0 1202. Therefore, asthe resistance of the NMOS transistors pulling down in_0 1202 increases,the capacitive loading on in_0 1202 decreases, keeping the “RC” valuefor this transition fairly constant across PVT variations.

Referring to FIG. 12, node in_l 1204 is connected to the input ofcapacitor circuit 1250, and the loading placed on node 1204 iscontrolled in a manner similar to that for capacitor circuit 1210 andin_0 1202. An additional consideration for this node is that it is alsoconnected to the inputs of the supplemental pull down cells in circuit1230.

Referring to FIG. 12 and FIG. 13, as the pull down impedance controlcode 226 changes, the capacitive load that supplemental cells 1300 placeon node in_l 1204 also changes. As PVT conditions change, the changes incapacitive loading that occur in capacitor circuit 1250 compensate forthe loading changes due the supplemental cells 1300 as well as forchanges in the resistance pulling down node in_l 1204.

Referring to FIG. 12 in combination with FIG. 11, when operating in25-ohm pull-down mode, the pull-down output circuits 1106 and 1108 sinka substantial current of within 10% of 30 mA for this particularembodiment (a power supply with 1.5 volts in combination with a 25-ohmpull down). Therefore, too-rapid a tuning-off of the pull down circuit204 could produce a very large “di/dt”, and therefore, a large groundbounce. Therefore, pull down circuit 204 is designed to turn off fairlyslowly in order to limit the “di/dt” and, therefore, the size of theground bounce. To accomplish this, transistor 1220 has a very long andnarrow channel, making it very resistive. The discharging of a logichigh voltage on node gt_pd2 1222 occurs through this resistivetransistor 1220. Therefore, node gt_pd2 1222 falls very slowly, turningoff transistor 1207 very slowly, keeping ground-bounce small.

To attain a linear ramping of current with time, thereby minimizing peak“di/dt”, the turning-off of NMOS transistor 1206 and 1207 are initiatedat somewhat different times and proceed at different rates. The turningoff of transistor 1207 begins later and occurs more slowly than that oftransistor 1206.

Turning On of the Pull down circuit

In general, in DTL systems, the turning on of a pull down circuit alwayslaunches a signal edge. Thus, referring to FIG. 12, the rate of turningon pull down circuit 204 is controlled by controlling the rate ofpulling-up of nodes in_0 1202 and in_l 1204. This is accomplished in thesame manner as the controlling of the rate of turning-off of the pulldown circuit 204.

Nodes in_0 1202 and in_l 1204 are pulled up by the PMOS transistors1022, 1002, 1004, 1006, 1016 and 1028 in the circuit shown in FIG. 10.The output resistance of transistors 1022, 1002, 1004, 1006, 1016 and1028 changes with PVT variations. However, the pull down code 226, usedin the adjustment of the capacitive loading on nodes in_0 1202 and in_l1204 tracks PVT resistance variations in NMOS transistors more closelythan in PMOS transistors. The PVT variations are similar between NMOSand PMOS transistors, but the process variations differ. The net resultis that the slew rate for the turning on of the pull down circuit 204 isnot quite as well-controlled as that for the turning off of the pulldown circuit 204, but well-enough to achieve gold overall performance.To attain a linear ramping of current with time, thereby minimizing peak“di/dt”, the turning on of NMOS transistors 1206 and 1207 are initiatedat somewhat different times and proceed at different rates. The turningon of transistor 1207 begins later and occurs more slowly than that oftransistor 1206.

Logic Considerations

Referring back to FIG. 2 in combination with FIG. 11, with the exceptionof sel_data_n 260, which determines whether the multiplexors 230, 240,and 250 accept data inputs or test inputs, a plurality of controlsignals, including signals up open 208 and down_25 210 affect only theoutputs of the flip flop circuits (not shown) within control circuit222. Referring to FIGS. 1 and 2, in general, when oe 220 is high, driver110 is in data driving mode; and when oe 220 is low, driver 110 is indata receiving mode. In data receiving mode, if up_open 208 is low,driver 110 terminates received signals. If up_open is high, driver 110presents a high impedance to the output and reflects received signals.In data driving mode, when the pull down impedance is intended to be 25ohms, input down_25 210 is set high. When the pull down impedance isintended to be 50 ohms, input down_25 210 is set low, and controlcircuit 222 functions to tri-state pull-down output unit 1106. Thesignal up_open 208 affects the output 206 only if oe 220 is low. I suchcase, if up_open 208 is low, pull up circuit 202 is active (i.e. couplesthe output 206 to VDDO) and the pull down circuit 204 presents a highimpedance to the output node 206. When up_open is high and oe 220 islow, both pull up circuit 202 and pull down circuit 204 are inactive(i.e. presenting a high impedance to output 206).

Other Embodiments

Other embodiments are within the following claims. For example, one ofordinary skill in the art appreciates that the stated limits areapproximations and a function of tolerances in power supply variation,in the number of supplemental bits employed, and a host of other factorsaffecting that the driver herein disclosed. Further, one of ordinaryskill in the art will appreciate that the driver circuitry may beimplemented in a complementary fashion whereby N-channel transistors arereplaced with P-channel transistors and vice versa, where appropriate.

Additionally, the driver alternatively includes either or both slew ratecontrol circuitry and impedance control circuitry within the driver.

Additionally, one skilled in the art appreciates that components withinboth the pull up circuit 202 and the pull down circuit 204 mayoptionally be represented by multiplexors. In one embodiment, forexample, pull up circuit 202 and pull down circuit 204 are representedby multiplexors wherein a control signal determines whether a data inputor a test input controls the output of the pull up and pull downcircuits 202 and 204. In another embodiment, components within both thepull up circuit 202 and the pull down circuit 204 are represented byinverting multiplexors.

In the present invention, a transistor may be conceptualized as having acontrol terminal which controls the flow of current between a firstcurrent handling terminal and a second current handling terminal. Anappropriate condition on the control terminal causes a current to flowfrom/to the first current handling terminal and to/from the secondcurrent handling terminal. In a bipolar NPN transistor, the firstcurrent handling terminal is the collector, the control terminal is thebase, and the second current handling terminal is the emitter. Asufficient current into the base causes a collector-to-emitter currentto flow. In a bipolar PNP transistor, the first current handlingterminal is the emitter, the control terminal is the base, and thesecond current handling terminal is the collector. A current exiting thebase causes an emitter-to-collector current to flow.

A MOS transistor may likewise be conceptualized as having a controlterminal which controls the flow of current between a first currenthandling terminal and a second current handling terminal. Although MOStransistors are frequently discussed as having a drain, a gate, and asource, in most such devices the drain is interchangeable with thesource. This is because the layout and semiconductor processing of thetransistor is symmretrical (which is typically not the case for bipolartransistors). For an N-channel MOS transistor, the current handlingterminal normally residing at the higher voltage is customarily calledthe drain. The current handling terminal normally residing at the lowervoltage is customarily called the source. A sufficient voltage on thegate causes a current to therefore flow from the drain to the source.The gate to source voltage referred to in an N channel MOS deviceequations merely refers to whichever diffusion (drain or source) has thelower voltage at any given time. For example, the “source” of an Nchannel device of a bi-directional CMOS transfer gate depends on whichside of the transfer gate is at a lower voltage. To reflect the symmetryof most N channel MOS transistors, the control terminal is the gate, thefirst current handling terminal may be termed the “drain/source”, andthe second current handling terminal may be termed the “source/drain”.Such a description is equally valid for a P channel MOS transistor,since the polarity between drain and source voltages, and the directionof current flow between drain and source, is not implied by suchterminology. Alternatively, one current handling terminal may bearbitrarily deemed the “drain” and the other deemed the “source”, withan implicit understanding that the two are not distinct, butinterchangeable.

What is claimed is:
 1. A driver configured to send and receive a signalon a transmission line, comprising: means for providing an outputimpedance; and means for controlling said means for providing saidoutput impedance to compensate for variations in said output impedance,said means for controlling also ensuring that a direct current impedanceof said means for providing is within a predetermined percentage of animpedance of said transmission line;
 2. The driver of claim 1, whereinsaid first transistor is diode connected.
 3. The driver of claim 1,wherein said plurality of first and second transistors is configured tomaintain a constant output impedance over a predetermined range ofvoltages.
 4. The driver of claim 1, wherein a net impedance of each ofsaid output elements remains approximately constant in response to achange in an output voltage of said driver.
 5. The driver of claim 1,wherein said means for controlling is configured to selectively enableor disable each of said output elements.
 6. The driver of claim 1,wherein said means for controlling is configured to selectively enableor disable each of said output elements in response to a change ofprocess, voltage and temperature conditions.
 7. The driver of claim 1,wherein said means for controlling is configured to selectively enableor disable each of said output elements by providing an impedancecontrol code to said means for providing.
 8. The driver of claim 7,wherein said impedance control code comprises a plurality of bits,wherein each bits corresponds to one of said plurality of outputelements.
 9. The driver of claim 1, wherein a number of output elementsselectively enabled or disabled is a function of said impedance of saidtransmission line, wherein selectively enabling an output elementrelates to a lower output impedance by said means for providing.
 10. Thedriver of claim 1, wherein said means for controlling is configured tocontrol said means for providing so that said output impedance issubstantially equal to said impedance of said transmission line when adriver output voltage is approximately half of a supply voltage of saiddriver.
 11. The driver of claim 1, further comprising: means fortransmitting and receiving a data signal on said transmission line. 12.The driver of claim 1, further comprising: means for providing alinearized relationship between an output current of said driver and anoutput voltage of said driver.
 13. The driver of claim 12, wherein saidmeans for providing said linearized relationship comprises a parallelcombination of a P-channel transistor and an N-channel transistor. 14.The driver of claim 13, wherein a gate node and a drain node of saidN-channel transistor have the same voltage.
 15. The driver of claim 1,wherein said means for providing comprises: a pull up circuit coupled toreceive at least one of a plurality of control codes, said pull upcircuit having a first impedance; and a pull down circuit coupled toreceive at least one of said plurality of control codes, said pull downcircuit having a second impedance.
 16. The driver of claim 15, whereinsaid pull up circuit comprises: a pull up output circuit; and a pull upparallel circuit, wherein said pull up output circuit and said pull upparallel circuit are controllable by said means for controlling tocontrol said first impedance.
 17. The driver of claim 16, wherein saidpull up output circuit comprises: a pull up gate voltage control circuitdriver, said pull up gate voltage control circuit comprising a pluralityof transistors; a buffer circuit coupled to said pull up gate voltagecontrol circuit; a pull up output element coupled to said pull up gatevoltage control circuit; and a slew rate control capacitor circuitcoupled to said pull up gate voltage control circuit.
 18. The driver ofclaim 16, wherein said parallel pull up circuit comprises: a pluralityof supplemental parallel pull up circuits, each of said supplementalparallel pull up circuits configured to receive at least one data signaland a bit of the plurality of control codes, said bit providing a pullup control signal to said supplemental pull up circuit.
 19. The driverof claim 18, wherein each supplemental pull up circuit comprises: asupplemental pull up output element; and a bit control circuit coupledto said supplemental pull up output element, said bit control circuitconfigured to bit of said supplemental pull up output element is active.20. The driver of claim 15, wherein said pull down circuit comprises: apull down output circuit; and a parallel pull down circuit, wherein saidpull down output circuit and said parallel pull down circuit arecontrollable by said means for controlling to control said secondimpedance.
 21. The driver of claim 20, wherein said pull down outputcircuit comprises: a pull down driver control circuit, said pull downdriver control circuit comprises an inverter, said inverter isconfigured to receive a data signal and provide an inverted data signal;a pull down output element coupled to said pull down driver controlcircuit; and a slew rate control circuit.
 22. The driver of claim 20,wherein said parallel pull down circuit comprises: a plurality ofsupplemental parallel pull down circuits, each of said supplementalparallel pull down circuits configured to receive at least one datasignal and a bit of the plurality of control codes, said bit providing apull down control signal to said supplemental pull down circuit.
 23. Thedriver of claim 18, wherein each supplemental pull down circuitcomprises: a supplemental pull down output element; a bit driver circuitcoupled to said supplemental pull down output element; and a bit controlcircuit coupled to said supplemental pull down output element, said bitcontrol circuit configured to bit of said supplemental pull down outputelement is active.
 24. The driver of claim 23, wherein said parallelpull down circuit comprises: a plurality of supplemental pull downoutput elements, each of said supplemental pull down output elementresponsive to said plurality of control codes; a bit driver circuitcoupled to said plurality of supplemental pull down and a bit drivercircuit coupled to said plurality of supplemental pull down outputelements.
 25. The driver of claim 1, further comprising: means forproving a slew rate control of an output of said driver under aplurality of process voltage and temperature (PVT) characteristics and aplurality of output voltages.
 26. The driver of claim 1, furthercomprising: means for ensuring driver quiescence in response to a corepower failure condition.